1. Introduction
  2. 1. Database
    1. 1.1. Hierarchy
    2. 1.2. Netlist
    3. 1.3. Layout
    4. 1.4. Fused Netlist & Layout
    5. 1.5. Reference Access
  4. 2. Geometry
    1. 2.1. Euclidean Geometry
    2. 2.2. Boolean Operations
    3. 2.3. Region Queries
  6. 3. Logic
    1. 3.1. BDD
  9. PDKs
  10. 4. Introduction
    1. 4.1. OpenSource PDKs
  13. Library
  14. 5. Introduction
    1. 5.1. Generate Standard-Cells
    2. 5.2. Generate Memory-Macros
  17. I/O & File Formats
  18. 6. File formats
    1. 6.1. LEF/DEF
    2. 6.2. OASIS
    3. 6.3. Verilog
    4. 6.4. Liberty
  21. Physical Synthesis
  22. 7. Introduction
  23. 8. Floorplan
    1. 8.1. Power Routing
    2. 8.2. Well Taps
    3. 8.3. IO Pads
  25. 9. Placement
    1. 9.1. Global Placement
    2. 9.2. Legalization
  27. 10. Buffer & tie-cell insertion
  28. 11. Routing
    1. 11.1. Maze Routing
    2. 11.2. Conflict Resolution
      1. 11.2.1. Rip-up & Reroute
      2. 11.2.2. Negotiation Based Algorithms
    4. 11.3. Hierarchical Routing
      1. 11.3.1. Global Routing
      2. 11.3.2. Resource Estimation
      3. 11.3.3. Multilevel Full-Chip Routing
    6. 11.4. Line-Probe Algorithms
  30. 12. Clock-Tree Synthesis
  31. 13. Timing Driven Place & Route
    1. 13.1. Static Timing Analysis
      1. 13.1.1. Wire Delay Estimation
    3. 13.2. Timing Driven Placement
    4. 13.3. Hold Time Fixing
    5. 13.4. Timing Optimization Strategies
  34. Verification
  35. 14. Netlist Extraction
  36. 15. Netlist Comparison
  38. Design For Test (DFT)
  39. 16. Scan-Chain Insertion
  40. 17. Automated Test-Pattern Generation
  42. Appendix

LibrEDA Book