Introduction
Database
Geometry
1. Euclidean Geometry
2. Boolean Operations
3. Region Queries
Logic
1. BDD
PDKs
Introduction
1. OpenSource PDKs
Library
Introduction
1. Generate Standard-Cells
2. Generate Memory-Macros
I/O & File Formats
File formats
1. LEF/DEF
2. OASIS
3. Verilog
4. Liberty
Physical Synthesis
Introduction
Floorplan
1. Power Routing
2. Well Taps
3. IO Pads
Placement
1. Global Placement
2. Legalization
Buffer & tie-cell insertion
Routing
1. Maze Routing
2. Conflict Resolution
3. 1. Rip-up & Reroute
  2. Negotiation Based Algorithms
4. Hierarchical Routing
5. 1. Global Routing
  2. Resource Estimation
  3. Multilevel Full-Chip Routing
6. Line-Probe Algorithms
Clock-Tree Synthesis
Timing Driven Place & Route
1. Static Timing Analysis
2. 1. Wire Delay Estimation
3. Timing Driven Placement
4. Hold Time Fixing
5. Timing Optimization Strategies
Verification
Netlist Extraction
Netlist Comparison
Design For Test (DFT)
Scan-Chain Insertion
Automated Test-Pattern Generation
Appendix

Clock-tree synthesis (CTS)

Clock-tree synthesis is the art of distributing clock and reset signals to the circuit components which need them. There are many requirements and many approaches.

H-tree

TODO

Example implementations

The arboreus-cts crate implements very simple algorithms for creating buffer trees. This is also useful for rebuffering of large-fanout nets and can be used for generating clock and reset trees - more for demonstration purposes though. There's no timing optimization involved yet.