Introduction
Database
Geometry
1. Euclidean Geometry
2. Boolean Operations
3. Region Queries
Logic
1. BDD
PDKs
Introduction
1. OpenSource PDKs
Library
Introduction
1. Generate Standard-Cells
2. Generate Memory-Macros
I/O & File Formats
File formats
1. LEF/DEF
2. OASIS
3. Verilog
4. Liberty
Physical Synthesis
Introduction
Floorplan
1. Power Routing
2. Well Taps
3. IO Pads
Placement
1. Global Placement
2. Legalization
Buffer & tie-cell insertion
Routing
1. Maze Routing
2. Conflict Resolution
3. 1. Rip-up & Reroute
  2. Negotiation Based Algorithms
4. Hierarchical Routing
5. 1. Global Routing
  2. Resource Estimation
  3. Multilevel Full-Chip Routing
6. Line-Probe Algorithms
Clock-Tree Synthesis
Timing Driven Place & Route
1. Static Timing Analysis
2. 1. Wire Delay Estimation
3. Timing Driven Placement
4. Hold Time Fixing
5. Timing Optimization Strategies
Verification
Netlist Extraction
Netlist Comparison
Design For Test (DFT)
Scan-Chain Insertion
Automated Test-Pattern Generation
Appendix

Legalization

Legalization transforms an approximate global placement solution into a legal placement solution. This means in practice: Remove overlaps between standard-cells/macro-blocks and place standard-cells on rows.

There are possibly constraints and optimization criteria, for example minimization of wiring length.

Example implementations

The following repositories contain legalization engines which can be used as inspiration for other implementations:

tetris-legalizer

LibrEDA Book

Legalization

Example implementations